Active very-high frequency circuit of the all-pass type utilizing an RC network whose capacitance is the gate-source capacitance of a FET

ABSTRACT

An all-pass type active circuit, realizable in the 8-12 GHz band has an inverting stage formed by a field effect transistor Q 1 , to whose gate the input signal V E  is applied through a resistor R constituting the resistance of an RC network, and whose gate-source capacitance C GS  is constitutes the capacitance C of the RC network. The parameters of a negative feedback branch inserted between the input V E  and the output V S  of the inverter, including a resistor R 0  and a transmission line L 0 , are chosen so that the elements of Z=R 0 , l=τv, R 0  =2/G M0 , where Z is the characteristic impedance of L 0 , l is the length of L 0 , v is the phase velocity of propagation, τ is the transit time of the electrons under the gate of Q 1  and G M0  is the transconductance of Q 1 . The phase shift between V E  and V S  at an operating frequency ω is a function of the time constant τ of the RC network. Two such all-pass type circuits, fed by a common input signal V E , and having different respective time constants τ 1 , τ 2 , provide a predetermined phase difference (90°) at ω between their respective outputs V S1 , and V S2 .

BACKGROUND OF THE INVENTION

1. Field of the Invention

The ivention relates to an active very-high frequency circuit of the all-pass type, comprising an amplifier stage and an RC network.

The invention finds its application in realizing image frequency rejection mixers intended, for example, for receiver front ends for signals relayed by artificial satellites or for microwave radio signals in general. The invention also finds its application in realizing modulators for four or more phases.

2. Discription of the Related Art

A phase-shift circuit is known from the publication entitled: "Monolithic RC All-Pass Networks with Constant-Phase-Difference Outputs" by Stephen K. ALTES et al. published in "IEEE Transactions on Microwave Theory and Techniques", VOL. MTT-34, No. 12, Dec. 1986, pp 1533-1537.

This document describes a phase-shift circuit realised on the basis of an RC network, comprising first of all two field effect transistors in a buffer arrangement for decreasing the output impedance of the stage preceding the RC network. Each of these transistors has its drain connected directly to a d.c. supply voltage, its source connected to ground through a resistor and has a considerable gate width (120 μm). Each transistor receives at its gate an input signal having the same amplitude as that of the signal received by another transistor but having the opposite phase.

The source of each of the transistors is also connected to one of the ends of a network formed by four parallel branches. Each branch is constituted by a series RC network. The outputs of the phase-shift circuit are connected to the node of the capacitor and the resistor of each branch. The resistors and capacitors of each branch are provided such that each output has the same amplitude and a phase difference of 90° relative to the next output. Furthermore, a switching circuit is provided for switching from one pair of outputs to another pair.

This circuit operates in the 220-280 MHz band, which frequency is much too low for the applications considered for this invention, these applications requiring a phase shifter operating at least in the 8-12 GHz band.

In the above publication a second circuit operating in the 3-5 GHz band is discussed. But this frequency domain is again too low for the applications under consideration. This result is achieved in this second circiut because it is a second-order circuit which is obtained by adding a certain number of components. A large number of components is still unfavourable for large scale integration which is searched for.

In addition, the second-order cirucuits have considerable insertion losses relative to first-order circuits. Moreover, its operation is based on the same principle as the above first-order circuit.

It is important to understand that in the prior-art circuits the load impedance of these circuits (or input impedance of the following circuit) appears in the transfer function so that the modulus (absolute value) of this transfer function depends on a time constant in which this impedance occurs, and on the frequency. The transfer function is thus that of a non-ideal all-pass function.

In order that the prior-art circuit(s) have a transfer function which is nearest possible to the ideal all-pass function, two conditions are to be fulfilled at the same time. First the output impedances of the buffered transistors are to be low with respect to the resistance of the RC network. Secondly, the input impedance of the next stage is to be high with respect to the impedance of the capacitor of the RC network.

Since the impedances of these preceding and following stages are fixed, the transfer function of the prior art network(s) can never be an ideal all-pass function, and this is more and more perceptible accordingly by as the frequency increases.

On the other hand, in each of the RC networks the values of the capacitor and resistor are fixed so as to obtain different time constants, allowing obtaining the desired phase shift on each path. From this it results first of all that the gain on each path is different. Then, if it is desired to increase the operating frequency, the result is that the RC products have to be diminished in order to diminish the time constants. Now we have seen hereinbefore that the resistor and capacitor values of the RC networks have to be maintained within certain boundaries imposed by the impendances of the preceding and following circuits, in order to remain as near to the ideal all-pass function as possible.

Under these conditions, the prior-art circuit(s) remains (remain) restricted to relatively low frequencies, or rather shows (show) very repidly degraded performance as regards amplitude and phase.

It is also important to understand that the prior-art circuit(s) always requires (require) two input signals having the same amplitude and opposite phase. On one hand the generation of these signals on the basis of a single signal requires the introduction of an additional circuit, which augments the surface of the network and its power consumption. On the other hand it is very difficult to obtain signals having exactly the same amplitude and opposite phase.

SUMMARY OF THE INVENTION

It is thus an object of the invention to provide an all-pass active circuit which has a substantially ideal all-pass transfer function.

This object is achieved by means of an active circuit of the RC-type as described in the preamble and characterized in that the amplifying stage comprises an inverting stage formed by a field effect transistor Q₁ arranged as an inverter, to whose gate a very high frequency input signal V_(E) is applied through a resistor R constituting the resistance of the RC network, and whose gate-source capacitance C_(GS) is used for constituting the capacitance C of the RC network, and in that the amplifying stage further comprises a negative feedback branck inserted between the very high frequency input V_(E) and the very-high frequency output V_(S) of the inverting stage, which negative feedback branch includes a resistor R₀ and a transmission line L₀, and in that the characteristic features of the elements of this circuit are interrelated by the following conditions in order to obtain an indeal all-pass transfer function:

a) Z=R₀

b) l=vτ

c) R₀ =2/G_(M0)

where Z is the characteristic impedance of the line L₀

l is its physical length

v is the phase velocity of propagation

τ is the transit time of the electrons under the gate of the inverting transistor Q₁ and

G_(MO) is the transconductance of the inverting transistor Q₁.

Under these conditions the circuit according to the invention can specifically attain frequencies of the order of 12 GHz or 18 GHz according to the technology employed for its realization.

In an embodiment of the circuit, the latter is characterized in that the gate source capacitance C_(GS) of the transistor Q₁ and the resistor R are furthermore provided for supplying a time constant τ₁ of the circuit havin a value to produce a relative phase difference of 45° between the very-high frequency input signal V_(E) and the very-high frequency output signal V_(S1) available at the drain of the inverting transistor Q₁.

In a further embodiment of the circuit, the latter is characterized in that the gate source capacitance C_(GS) of the transistor Q₁ and the resistor R are furthermore provided for supplying a time constant τ₂ of the circuit having a value to produce a relative phase difference of 135° between the very-high frequency input signal V_(E) and the very-high frequency output signal V_(S2) available at the drain of the transistor Q₁.

One of the objects of the invention is also to provide an active 0°-90° phase shifter operating at very high frequencies on the basis of a single input signal, and showing good performance as regards amplitude deviation and phase deviation.

According to the invention, a phase-shift circuit for supplying two very-high frequency output signals V_(S1) and V_(S2) having the same amplitude and a relative phase difference of 90° on the basis of a single very-high frequency input signal V_(E) is constituted by an all-pass circuit in accordance with the first embodiment coupled via the input V_(E) to an all-pass circuit in accordance with a second embodiment.

Under these conditions, this phase-shift circuit operates at very high frequencies mentioned hereinbefore, but it also supplies output signals of the same amplitude with a precision of ±0.1 dB, and whose phase difference is 90° with a precision of ±0.6°, all this on the basis of a single input signal.

One of the objects of the invention is also to provide an all-pass circuit and a phase-shift circuit, which may both be integrated, for example on gallium arsenide, a semiconductor material which is particularly favourable for very-high frequency realizations, in a manner such that and the circuits can be fabricated in combination with other very-high frequency circuits.

In a preferred embodiment this network and this circuit are realized by means of field effect transistors of the MESFET type for a maximum operating frequency of the order of 12 GHz, and by means of field effect transistors of the HEMT type for a maximum operating frequency of the order of 18 GHz, and integrated with the other elements on gallium arsenide (GaAs).

BRIEF DISCRIPTION OF THE DRAWING

The invention will be better understood by means of the following description illustrated by the annexed drawing figures of which:

FIG. 1a diagrammatically represents an all-pass RC cell according to the invention,

FIG. 1b represents the equivalent circuit of the circuit as shown in FIG. 1a.

FIG. 2 represents a 0°-90° phase-shift circuit constituted by two all-pass cells as shown in FIG. 1, admitting the same input signal,

FIG. 3a represents, plotted against the frequency f(GHz), the amplitude difference ΔA (in 10⁻² dB) and the phase difference Δφ in degrees, for an optimum value of the negative feedback resistor R₀,

FIG. 3b represents the same variables for a value of the negative feedback resistor R₀ which is smaller than the optimum value,

FIG. 3c represents the same variables for a value of the negative feedback resistor R₀ which exceeds the optimum value,

FIG. 4a respresents, plotted against frequency, the amplitude and phase variations of the input impedance Z_(I) of the phase-shift circuit realized by means of the HEMT transistors, and

FIGS. 4b and 4c represent, plotted against frequency, the respective amplitude and phase variations of the output impedances Z_(S1) and Z_(S2) of the outputs of the phase-shift realized by means of the HEMT transistors.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

For the intended applications at very high frequencies, the all-pass circuit according to the invention as well as the phase-shift circuit formed on the basis of this all-pass circuit, are realized by means of field effect transistors, on a semiconductor substrate of the group III-V, for example, on gallium arsenide (GaAs).

FIG. 1a diagrammatically shows the all-pass cell according to the invention. This cell comprises an inverting stage formed by the inverting transistor Q₁ and a load Q₃. The drain of the inverting transistor Q₁ is connected to a d.c. supply voltage V_(DD) across the load Q₃ and its source is directly connected to ground.

The transistor Q₁ exhibits a gate-source capacitance designated by C_(GS).

This cell also includes an RC network formed by the resistor R whose one end is connected to the gate of the inverting transistor Q₁ and whose other end is connected to the very-high frequency input V_(E) of the circuit, and formed by the gate-source capacitance C_(GS) of the transistor Q₁.

Whereas this RC network is connected to the input of the all-pass cell according to the invention, the transfer function of this cell does not depend on the output impedance of the preceding stage, as was the case in the networks known from the state of the art.

The load Q₃ is formed preferably by a field effect transistor whose gate is biased through a resistor R_(A) by a d.c. voltage V₃, whose drain is connected directly to the d.c. supply voltage V_(DD) and whose source is connected to the drain of the inverting transistor Q₁ constituting the output node 1 of the cell at which the output signal V_(S) is available. The gate of the load transistor Q₃ is further connected to its source via a capacitor C₁.

According to the invention, the stage described above is arranged as a negative feedback amplifier by means of a branch inserted between the input V_(E) at node 4 and the output V_(S) at node 1. This branch comprises a resistor R₀ and a transmission line L_(O) arranged in series.

This negative feedback branch is isolated from input 2 V_(E) by a capacitor C₂ inserted between the nodes 2 and 4 and from the branch R-C_(GS) by a capacitor C₃ inserted between the nodes 4 and 3. On the other hand, the gate of the inverting transistor Q₁ is biased by a d.c. voltage V₁ through a resistor R_(B) inserted between V₁ and the end of the resistor R in the R-C_(GS) network at node 3.

The bias voltages V₁ and V₃ are provided variably so as to allow of adjusting the amplitude and the phase of the output signal V_(S).

In order to obtain the transfer function of an ideal all-pass cell, conditions are imposed on the elements of the cell, which conditions will be better understood when considering the equivalent diagram of this circuit represented in FIG. 1b together with the diagram of FIG. 1a.

                  TABLE I                                                          ______________________________________                                          ##STR1##                      (1)                                             G.sub.M  =  G.sub.MO  e.sup.-jωτ                                                                    (2)                                              ##STR2##                      (3)                                              ##STR3##                                                                       ##STR4##                                                                                                     (4)                                              ##STR5##                      (5)                                              ##STR6##                      (6)                                              ##STR7##                      (7)                                              ##STR8##                      (8)                                              ##STR9##                      (9)                                             ______________________________________                                    

                  TABLE II                                                         ______________________________________                                         Condition a:        Z = R.sub.0                                                Condition b:        l = τV                                                 Condition c:        R.sub.0 = 2/G.sub.MO                                       ______________________________________                                    

In FIG. lb the line L₀ is distinguished by its physical length l by its electrical length Φ given by equation (1) of Table I, where β is the phase constant of the line, f is the operating frequency and v is the phase velocity of propagation, and distinguished by its characteristic impedance Z;

Y is the load constituted by the admittance of the input signal to the stage (or circuit) following the all-pass cell;

G_(D1) and G_(D3) are the drain-source conductances of the transistors Q₁ and Q₃ respectively, and G_(D) their equivalent conductance; and

G_(MO) is the transconductance of the transistor Q₁, and τ is the transit time of the carriers under the gate of this transistor, which results in the fact that the transconductance G_(M) of the inverting stage is given by equation (2) of Table I.

Under these conditions the transfer function of the all-pass unit cell of FIG. 1a is given by equation (3) of Table I, in which equation C_(GS) has been written as C for simplicity.

As a first condition will be chosen to realized R₀ =Z (condition a). The transfer function of the all-pass cell can thus be written more simply in form of the equation (4) of Table I.

The condition a is fulfilled when the characteristic impedance Z of the line L₀ is chosen to be equal to the resistor R_(O) of the negative feedback branch.

As a second condition will be chosen

    Φ=∩τ (knowing that ω=2πf)

Thus, equation (1) of the Table I leads to writing this second equation in the form of:

    =l v τ                                                 (condition b).

Condition b is fulfilled when the physical length l of the line L₀ produces a delay which compensates for the signal delay between the input and the output of the inverting stage.

As a third condition will be chosen

    R.sub.0 =2/G.sub.MO                                        (condition c)

Condition c is fulfilled when, in addition, the resistor R₀ of the negative feedback branch is chosen to have the value of two times the inverse of the transconductance of inverting transistor Q₁.

The transfer function of the all-pass unit cell according to the invention can thus be described in the form of equation (5) of the Table I.

As shown in equation (5) of the Table I the transfer function F(jω) is written in the form of the function of an ideal all-pass (see term (6) of the Table I) which is multiplied by a constant independent of the value of the resistor R and of the capacitor C of the RC network (see term (7) of Table I).

Under these conditions, the amplitude of F(jω) certainly depends on the frequency, but it does not depend on the values of R and C, worded differently, the amplitude of the output signal does not depend on the time constant of the RC network.

The circuit comprises a single parasitic element which is the gate-drain capacitance of the inverting transistor Q₁. But this element is of minor importance because this gate-drain capacitance is very weak with respect to the gate-source capacitance of the field effect transistor.

The gate-drain capacitance is thus practically short-circuited by the gate-source capacitance.

The gate-source capacitance C=C_(GS) of the transistor Q₁ is a function of the dimensions of this transistor. To increase the operating frequency of the circuit, one may either diminish the size of the inverting transistor Q₁, or diminish the resistance R of the RC network, which allows of diminishing the time constant of the circuit.

If one wishes to diminish the capacitance C by diminishing the gate width W of the transistor Q₁, the transconductance G_(MO) will diminish. In order to fulfill the condition c (see Table II), the resistance R₀ of the negative feedback branch thus has to increase, which entails that for fulfilling the condition a (see Table II) the characteristic impedance Z of the line has to increase. The increasing of the characteristic impedance Z of the line L₀ may be obtained by diminishing the line width.

If one chooses to realize the circuit on gallium arsenide, which is a particularly favourable material for forming very-high frequency networks, the maximum characteristic impedance which may be obtained for a line is of the order of 100 to 120 Ω as a result of the edge effect of the line.

On this same material the lower limit of the value of the resistor R is situated around 30 or 40 Ω in order to properly control the exact value of this resistor. Actually, any transistor such as Q₁ to which the resistor R is connected, has gate contacts showing a given resistance, and the resistance R of the RC network is to remain large relative to the resistance of the gate contact of the inverting transistor Q₁.

The circuit according to the invention can be realised either by means of field effect transistors of the MESFET type or by means of field effect transistors of the HEMT type. The latter transistors are preferred for obtaining circuits operating at higher frequencies because their transconductance is on average two times higher than that of the former transistors.

The bias voltage V₁ can be adjusted to make the transconductance G_(M) of the inverting stage vary. In order to verify the condition c, this allows of adjusting the value of the negative feedback resistor R₀ in the case in which the latter would differ from the optimum value, for example, owing to the dispersion of the components during the realization of the circuit.

The bias voltage V₃ is provided for fixing the drain current of the inverting transistor Q₁ so as to adjust the quiescent point.

According to the invention, a 0°-90° phase shifter can furthermore be realized on the basis of the all-pass unit cell described above. In order to realize this phase shifter, two cells of the type of this all-pass cell are coupled by means of their input node 2. Consequently, this phase shifter operates by means of a single input V_(E).

As represented in FIG. 2, this phase shifter thus comprises the two cells A and B respectively.

Each cell comprises an inverting transistor Q₁, Q₂ ; a load transistor Q₃, Q₄ ; an RC network formed by the resistor R₁ and the gate-source capacitance C₁ =C_(GS1) of Q₁ for A; an RC network formed by the resistor R₂ and the gate-source capacitance C₂ =C_(GS2) of Q₂ for B; a negative feedback branch formed by the resistor R₀₁ and the transmission line L₀₁ for A; a negative feedback branch formed by the resistor R₀₂ and the transmission line L₀₂ for B.

In A, for the load Q₃, the gate bias voltage is V₃ and the bias resistor is R_(A1), and for the inverter Q₁ the gate bias voltage is V₁ and the bias resistor is R_(B1).

In B, the load is Q₄, of which the gate bias voltage is V₄ and the bias resistor is R_(A2) ; and the inverter is Q₂ of which the gate bias voltage is V₂ and the bias resistor is R_(B2).

The isolation capacitors C₁, C₂, C₃ of the unit cell described hereinbefore become C₁₁, C₁₂, C₁₃ and C₂₁, C₂₂, C₂₃ respectively, in the cells A and B.

The output signals V_(S1) and V_(S2) occur at the points 10 and 20 at the drains of the inverting transistors Q₁ and Q₂ respectively.

The values of the elements of each of the RC networks in the cells A and B are chosen for producing the respective time constants

    π.sub.1 and τ.sub.2

which allow of obtaining, on the basis of the very-high frequency input signal V_(E) common to the two cells, very-high frequency output signals V_(S1) and V_(S2) which, relative to the input signal V_(E), have

a 45° phase shift for the cell A

a 135° phase shift for the cell C.

This is obtained with:

    ωτ.sub.1 ω0.6

    ωτ.sub.2 ω3.7

Under these conditions, the output signals V_(S1) and V_(S2) show a 90° phase shift relative to one another.

The transfer functions of each of the cells A and B respectively, are given by the equations (8) and (9) of the Table I. These functions show that the amplitude deviation does not depend on the time constants of the cells.

Table II recalls the conditions a, b, c imposed on the two respective cells and the following Tables III and IV are pertinent to this discussion:

                  TABLE III                                                        ______________________________________                                                                 Optimum value                                          R.sub.0 = R.sub.01 = R.sub.02 (Q)                                                            105       116.75      130                                        ______________________________________                                         Amplitude     -0.04     -0.08       0.1                                        difference ΔA(dB)                                                                      0.07      0.07        0.02                                       maximum phase 92.7      90.5        89.4                                       difference                                                                     Δφ (degrees)                                                         minimum phase 91.1      89.3        88.2                                       difference                                                                     D.C.    E.sub.1   6         6         6                                        voltages                                                                               V.sub.1   -0.02     -0.23     -0.36                                    (volts) V.sub.2   0.02      -0.23     -0.44                                            V.sub.3   2.85      2.85      2.85                                             V.sub.4   2.85      2.85      2.85                                     ______________________________________                                    

                                      TABLE IV                                     __________________________________________________________________________     COMPONENTS    ALL-PASS A    ALL-PASS B                                         __________________________________________________________________________     HEMT type transistor                                                                         Q.sub.1                                                                               Q.sub.3                                                                               Q.sub.2                                                                               Q.sub.4                                     Gate length = L.sub.g = 0,6 μm                                              Gate width W  W.sub.1 = 70 μm                                                                    W.sub.3 = 50 μm                                                                    W.sub.2 = 70 μm                                                                    W.sub.4 = 50 μm                          Number of gate fingers N                                                                     N.sub.1 = 2                                                                           N.sub.3 = 1                                                                           N.sub.2 = 2                                                                           N.sub.4 = 1                                 Resistors:    R.sub.A1 = 10 kQ                                                                             R.sub.A2 = 10 kQ                                                 R.sub.B1 = 10 kQ                                                                             R.sub.B2 = 10 kQ                                                 R.sub.1 = 51.9 Q                                                                             R.sub.2 = 394 Q                                                  R.sub.01 = 116.75 Q                                                                          R.sub.02 = 116.75 Q                                Capacitors:   C.sub.01 = 0.5 pF                                                                            C.sub.02 = 0.5 pF                                                C.sub.11 = 10 pF                                                                             C.sub.12 = 10 pF                                                 C.sub.21  = 2 pF                                                                             C.sub.22 = 2 pF                                    Transmission Line                                                                        Height                                                                             h = 100 μm h = 100 μm                                      on gallium                                                                               Width                                                                              W = 5 μm   W = 5 μm                                        arsenide GaAs                                                                            Length                                                                             l = 359 μm l = 359 μm                                                    E.sub.1 = 6 V                                                    D.C. voltages V.sub.1 = -0.23 V                                                                            V.sub.2 = -0.23 V                                                V.sub.3 = 2.85 V                                                                             V.sub.4 = 2.85 V                                   __________________________________________________________________________

Table III shows the results obtained by means of a phase-shift circuit according to the invention, constituted by the elements of Table IV, that is, realised on gallium arsenide by means of HEMT transistors.

Table III specifically shows the amplitude difference ΔA between the signals V_(S1) and V_(S2) when the negative feedback resistor R₀ (R₀₁ and R₀₂ respectively) has the optimum value of 116.75 Q and when, owing to the dispersion, it would have the value of 105 Q, or 130 Q, Table III also shows the maximum phase shift and the minimum phase shift corresponding with the above values of the resistor R₀. In this Table III it will be noted that in order to compensate for the deviation of R₀, the values of the bias voltages V₁ and V₂ respectively, have been adjusted.

Table IV shows maximum values of the components for realising the network according to the invention with transistors of the HEMT type.

FIG. 3a represents, by means of the solid line curve, the difference in amplitude ΔA in 10⁻² dB between the two output signals V_(S1) and V_(S2) of a 0°-90° phase shifter realized in accordance with the invention and by means of optimum value components entered in the Tables III and IV, this curve being plotted against the frequency f in GHz; and by means of the dashed-line curve, the phase difference Δφ between the signals of the outputs V_(S1) and V_(S2) also plotted against the frequency f in GHz.

    R.sub.0 =116.75ω

    V.sub.1 =-0.23 V

    V.sub.2 =-0.23 V

This FIG. 3a shows that, in the 8-12 GHz frequency band and when the phase shifter is realized on gallium arsenide by means of HEMT transistors, the phase difference Δφ between the two outputs is 90°±0.6°, and that the amplitude difference ΔA is less than ±0.1 dB.

FIG. 3b represents by means of the solid line curve, the amplitude difference ΔA under the conditions for which the negative feedback resistor R_(O) falls short of the optimum value (see Table III).

    R.sub.0 =105 Ω

    V.sub.1 =-0.02 V

    V.sub.2 =0.02 V

and the dashed line curve represents the phase difference Δφ.

This FIG. 3b shows that when adjusting the gate bias voltages of the inverting transistors Q₁ and Q₂, the errors in the phase and amplitude differences which appear owing to the error at R_(O) may be minimized. Under these conditions, between 8 and 12 GHz, the phase difference was situated between 91° and 92°7; and the amplitude difference was less than ±0.1 dB.

FIG. 3c represents, by means of the solid-line curve, the amplitude difference ΔA for the conditions in which the negative feedback resistor R₀ has a value exceeding the optimum value (see Table III)

    R.sub.0 =130 Ω

    V.sub.1 =-0.360 V

    V.sub.2 =-0.440 V

and the dashed line represents the phase difference Δφ.

This FIG. 3c shows that when the bias voltages V₁ and V₂ are adjusted, the errors in the phase and amplitude differences may be minimized. Under these conditions, between 8 and 12 GHz, the phase difference Δφwas situated between 88°2 and 89°4. The amplitude difference was less than ±0.1 dB.

Generally speaking, these results show that the preferred operating frequency of the circuit realized on gallium arsenide by means of HEMT transistors will be situated in the 8 to 12 GHz band with the components of Table IV. But, by changing the dimensions of HEMT transistors, one could obtain a correct operation to within the 10-18 GHz band.

Owing to the fact that the circuit according to the invention is a negative feedback amplifier, the well-advised choice of the elements allows of achieving that the input impedance Z_(I) of the phase shifter is of the order of 50 ω, in the 8 to 12 GHz frequency band considered for the preceding embodiment.

For this purpose, the FIG. 4a shows the amplitude A(Z_(I)) of the input impedance of the phase shifter in this embodiment as well as the phase φ(Z_(I)) of this impedance of this frequency band.

Due to the well-advised choice of these same elements, the output impedance Z_(S1) of the cell A of the phase shifter and the output impedance Z_(S2) of the cell B of the phase shifter remain

between 83 and 84 ω for the first impedance

between 86 and 91 ω for the second impedance.

                                      TABLE V                                      __________________________________________________________________________     COMPONENTS    ALL-PASS A    ALL-PASS B                                         __________________________________________________________________________     MESFET type transistor                                                                       Q.sub.1                                                                               Q.sub.3                                                                               Q.sub.2                                                                               Q.sub.4                                     Gate length = Lg = 0,7/μm                                                   Gate width W  W.sub.1 = 70 μm                                                                    W.sub.3 = 50 μm                                                                    W.sub.2 = 70 μm                                                                    W.sub.4 = 50 μm                          Number of gate fingers N                                                                     N.sub.1 = 2                                                                           N.sub.3 = 1                                                                           N.sub.2 = 2                                                                           N.sub.4 = 1                                 Resistors:    R.sub.A1 = 10 kQ                                                                             R.sub.A2 = 10 kQ                                                 R.sub.B1 = 10 kQ                                                                             R.sub.B2 = 10 kQ                                                 R.sub.1 = 50 Q                                                                               R.sub.2 = 400 Q                                                  R.sub.01 = 209 Q                                                                             R.sub.02 = 209 Q                                   Capacitors:   C.sub.01 = 0.5 pF                                                                            C.sub.02 = 0.5 pF                                                C.sub.11 = 10 pF                                                                             C.sub.12 = 10 pF                                                 C.sub.21 =  2 pF                                                                             C.sub.22 = 2 pF                                    Transmission Line                                                                        Height                                                                             h = 100 μm h = 100 μm                                      on gallium                                                                               Width                                                                              W = 5 μm   W = 5 μm                                        arsenide GaAs                                                                            Length                                                                             l = 359 μm l = 359 μm                                                    E.sub.1 = 6 V                                                    D.C. voltages V.sub.1 = -0.23 V                                                                            V.sub.2 = -0.23 V                                                V.sub.3 = 2.85 V                                                                             V.sub.4 = 2.85 V                                   __________________________________________________________________________

Thus, the FIGS. 4b and 4c show the respective amplitudes A(Z_(S1)) and A(Z_(S2)) of these output impedances, as well as the respective phases φ(Z_(S1)) and φ(Z_(S2)) of these impedances always in the above-described embodiment and for the same frequency band.

The output impedances of the phase shifter are thus of the order of two times the value of the input impedance.

The curves of the FIGS. 4a, 4b, 4c have been plotted for the cases in which the values of the phase shifter elements are optimal.

In another embodiment of the invention, in which one wishes to use MESFET transistors, for example, in order to fabricate them in combination with other associated circuits, then the maximum frequencies will be situated in the 8 to 12 GHz band.

The Table V below shows a set of characteristic values for realising the circuit according to the invention by means of MESFETs. It is to be noted that the transistors Q₁ and Q₂ of the inverters preferably have 2 gate fingers:

The performance of such a circuit realised by means of MESFETs is also very good as regards amplitude difference and phase difference of the two output signals V_(S1) and V_(S2).

It is to be noted that, in each of the embodiments of the invention, the inverting transistors Q₁ and Q₂ have been chosen to be identical in order to simplify the manufacture of the circuit, in the same way as the lines L₀₁ and L₀₂. Thus, the manufacturing efficiency of the phase shifter is improved. 

We claim:
 1. An active very-high frequency circuit of the all-pass type, comprising an inverting stage having an input for a very-high frequency input signal V_(E) and an output for a very-high frequency output signal V_(S), said inverting stage having a transfer function relating said output signal V_(S) to said input signal V_(E) which depends on a time constant equal to the product of a resistance and a capacitance of an included RC network, the inverting stage comprising a field effect transistor Q₁ whose drain-source path is in a series path with a load, said output signal V_(S) being formed at a first point in said series path intermediate said drain-source path and said load, said first point being coupled to said output for said output signal V_(S), and whose gate is coupled via a resistor R constituting the resistance of the RC network to a second point which is coupled to the input for said input signal V_(E), and whose gate-source capacitance C_(GS) constitutes the capacitance C of the RC network, and further comprising a feedback branch coupled between the first point and the output for said output signal V_(S), which feedback branch includes, in cascade, a resistor R_(O) and a transmission line L_(O), wherein parameters of the feedback branch are interrelated by the following conditions:a) Z=R_(O) b) l=τv c) R_(O) =2/G_(MO) where: Z is the characteristic impedance of the line L_(O) l is its physical length v is the phase velocity of propagation τ is the transit time of the electrons under the gate of the inverting transistor Q₁ and G_(MO) is the transconductance of the transistor Q₁.
 2. A circuit as claimed in claim 1, wherein said first point is at the drain of the transistor Q₁ which drain is coupled to a d.c. supply voltage input E₁ via said load, and wherein said load is an active load formed by a field effect transistor Q₃, whose drain is connected to the d.c. supply voltage input E₁, whose source is connected to the drain of transistor Q₁ and whose gate is biased through a resistor R_(A) coupled to a d.c. voltage input V₃, the gate of transistor Q₃ being further coupled to its source via a capacitor C₁.
 3. A circuit as claimed in claim 2, wherein the gate of the transistor Q₁ is biased by a d.c. voltage input V₁ through a resistor R_(B) connected between a third point and the d.c. voltage input V₁ and the resistor R being coupled between said third point and the gate of transistor Q₁, the input for the very-high frequency input signal V_(E) being coupled to the second point by a capacitor C₂, and the said second and third points being coupled via a capacitor C₃, whereby, in order to fulfill the condition c), a compensation of the value G_(MO) is obtained by variation of the input voltage V₁ in case the resistor R₀ has a value which is slightly different from an optimal value.
 4. A circuit as claimed in claim 3, wherein the physical length l and a width W of the transmission line L₀ are chosen in a manner such that the conditions a) and b) are fulfilled.
 5. A circuit as claimed in claim 4, characterized in that a width W_(G) of the gate of the transistor Q₁ is arranged for providing the transconductance G_(MO) to filfill the condition c).
 6. A circuit as claimed in claim 5, wherein the gate-source capacitance C_(GS) of the transistor Q₁ and and resistor R are chosen for providing a time constant τ₁ of the network which produces a relative phase difference of 45° between the very-high frequency input signal V_(E) and the very-high frequency output signal V_(S).
 7. A circuit as claimed in claim 5, wherein the gate-source capacitance C_(GS) of the transistor Q₁ and the resistor R are furthermore arranged for providing a time constant τ₂ of the network which produces a relative phase difference of 135° between the very-high frequency input signal V_(E) and the very-high frequency output signal V_(S).
 8. A phase shift circuit for producing, in response to a single very-high frequency input signal V_(E), two very-high frequency output signals V_(S1) and V_(S2) having substantially the same amplitude and a relative phase difference of substantially 90°, this phase-shift circuit comprising first and second all-pass circuits of the same type having a common input for the input signal V_(E) and respective outputs for the output signals V_(S1) and V_(S2), said first and second all-pass circuits comprising respective inverting stages with respective transfer functions relating the respective output signals V_(S1) and V_(S2) to said input signal V_(E) dependent upon respective time constants τ₁ and τ₂ equal to the product of a resistance and a capacitance of associated respective RC networks chosen to produce the relative phase difference of 90° between the output signals V_(S1) and V_(S2), said respective inverting stages comprising respective field effect transistors Q₁ whose drain-source paths are in respective series paths with respective loads, said respective output signals V.sub. S1 and V_(S2) being formed at respective first points in said respective series paths intermediate said respective drain-source paths and said respective loads, said respective first points being coupled to said respective outputs for the output signals V_(S1) and V_(S2), and whose gates are coupled to respective second points coupled to said common input via respective resistors R₁, R₂ constituting the resistances of the respective associated RC networks and whose gate-source capacitances C_(GS) constitute the capacitances C of the respective associated RC networks, respective feedback branches coupled between the respective second points and the respective outputs for the signals V_(S1) and V_(S2), each feedback branch including, in cascade a resistor R₀ and a transmission line L_(O), and wherein the parameters of the each feedback branch are interrelated by the following conditions:a) Z=R_(O) b) l=τv c) R_(O) =2/G_(MO) where: Z is the characteristic impedance of the line L_(O) l is its physical length v is the phase velocity of propogation τ is the transit time of electrons under the gate of the respective transistor Q₁ and G_(MO) is the transductance of the respective transistor Q₁.
 9. A circuit as claimed in claim 1, wherein the field effect transistor Q_(l) is of the HEMT or MESFET type, integrated, as are the other elements of the circuit, on a gallium arsenide substrate (GaAs).
 10. A circuit as claimed in claim 8, wherein the field effect transistors Q₁ are of the HEMT or MESFET type, integrated, as are the phase-shift other elements of the circuit, on a gallium arsenide substrate (GaAs).
 11. A circuit as claimed in claim 10, wherein the input impedance at the input for V_(E) is of the order of 50 Ω, and in that the output impedance at each of the outputs for signals V_(S1) and V_(S2) is of the order of twice this input impedance. 